化学翻译大师帮我下，我做毕业设计急着交
HfO2 and Al2O3 gate dielectrics on GaAs grown by atomic layer deposition
Metal-oxide-semiconductor field-effect transistors
sMOSFETsd on III–V semiconductor would offer a number
of advantages over Si-based devices. The higher carrier mobility
would lead to faster complementary MOS sCMOSd
logic operation, higher breakdown fields would support highpower/
temperature applications, band structure engineering
would offer design flexibility, and monolithic optoelectronic
circuits would likely become manufacturable.
However, MOSFETs on high-carrier-mobility substrates
scompound semiconductors as well as germaniumd have
been elusive due to the lack of high-quality gate insulators,
mostly because of the absence of stable passivating native
oxides and the high density of slow interface traps sDitd with
deposited oxides.1 For example, Fermi level pinning upon
GaAs oxidation has been attributed to oxygen-induced displacement
of surface As atoms, where doubly O-coordinated
second-layer Ga atoms give rise to gap states.2 Excess interfacial
As occupying AsGa antisite defects causes gap states as
well.2,3 Such As may be formed via decomposition of As2O3
in the vicinity of GaAs, resulting from the reaction: As2O3
+2GaAs!Ga2O3+4As.4 Until recently, oxide/III–V interfaces
with low Dit had to be fabricated by molecular beam
epitaxy sMBEd of Ga2O3 swhere Gd was added to reduce
leakaged1,5 or Al2O3.6 Fermi level unpinning in the
Ga2O3 /GaAs system has been attributed to a
Ga2O/GaAs-like interface in which the Ga and As surface
atoms are restored to near-bulk charge.2
Atomic layer deposition sALDd or chemical vapor deposition
sCVDd is technologically more attractive than MBE.
The recent development of high-quality ALD- and CVDgrown
high-permittivity shigh- kd gate dielectrics on Si justi-
fies some optimism regarding integration on III–Vsubstrates.7 Gate stacks for depletion mode MOSFETs with
Dit,1012 cm−2 eV−1 were recently fabricated by ALD of
Al2O3 onto native oxide covered GaAs.8–10 A 600–650 °C
anneal in O2 minimized current–voltage hysteresis and frequency
dispersion, and maximized gate stack capacitance.
Transmission electron microscopy sTEMd pointed to a remarkably
sharp Al2O3 /GaAs interface, prompting the speculation
that the native oxide is removed during the ALD process.
ALD-grown Al2O3 also results in good gate stack
properties on InGaAs11 and AlGaN/GaN12 and may be used
to coat compound semiconductor nanowires conformally.13
By contrast, very few studies have been published regarding
the most important high- k gate dielectric, HfO2, on III–V
semiconductors.14,15
参考答案:粘贴过来太乱了，很多缩写变形了，出现很多“s”“d”等无用字符，不过认真纠正过来了。
砷化镓原子层沉积法产生氧化铪和氧化铝闸极介电层
III–V半导体上使用的金属氧化物半导体场效应晶体管（MOSFETs）和硅基器件相比有很多优势。高的载流迁移率会导致互补性金属氧化物半导体（CMOS）逻辑运算更快，更高击穿场强支持其在大功率/高温方面的应用，能带结构工程提供了设计灵活性，单片光电集成电路使可生产性提高。然而，高载流迁移率的基体复合半导体及锗半导体上的金属氧化物半导体场效应却因缺乏高质量的栅极绝缘层而不能利用， 很大程度上是由于稳定钝化的俱生氧化层的缺失，以及高密度界面缺陷（Dit）随着沉积了氧化物（1）。例如，砷化镓氧化的费米能级钉扎效应归于氧诱导的表面砷原子的位移，而双层氧原子结合的双层镓原子产生了间隙状态（2）。过量的表面砷原子占据了砷化镓对位的缺陷也能造成间隙状态（2,3）。这类砷可通过砷化镓邻近的硫化砷的分解反应来形成，反应如下：
As2O3（氧化砷）+2GaAs（砷化镓）=Ga2O3（氧化镓）+4As（砷）（4）。
最近界面缺陷密度较低的氧化物/III–V型界面用氧化镓的分子束外延（MBE）来补偿（3），而加入镓来减少泄露（1,5）或降低氧化铝含量（6）。氧化镓/砷化镓体系中的费米能级钉扎效应归于一种氧化镓/砷化镓样的界面，在该界面上镓和砷表面的原子以大量电荷储存（2）。原子层沉积法（ALD）或化学气相沉积（CVD）在技术上比分子束外延(MBE)更有前景。采用高质量原子层沉积和化学气相沉积在硅上产生高介电系数值的闸极介电层取得的最新进展使III–V基体的集成方面得到优化（7）。界面缺陷密度为（1012 cm[负2次方] eV[−1次方]）的耗尽型金属氧化物半导体场效应晶体管的闸极堆栈最近通过采用原子层沉积法把氧化铝沉积到俱生氧化层覆盖的砷化镓上得到解决（8–10）。氧气中600–650 °C的退火使电流-电压滞环和频率色散度最小化并使闸极堆叠式电容最大化。透射电镜（TEM）显示了明显锐化的氧化铝 /砷化镓界面，因此推测俱生氧化层在原子层沉积过程得以去除。原子层沉积的氧化铝也形成了砷化镓（11）和铝镓氮/氮化镓（12）的良好的闸极堆栈特性，或许可用来等形涂布复合半导体纳米线（13）。比较而言，有关III–V 半导体应用中最重要的高介电值闸极介电物氧化铪的研究鲜见发表（14,15）。